1. Technical Field
Embodiments of the present disclosure relate to semiconductor devices and semiconductor systems including the same.
2. Related Art
Fast semiconductor memory devices with improved integration density are increasingly in demand. Synchronous memory devices operating in synchronization with external clock signals have been revealed to improve the operation speed thereof.
At first, single data rate (SDR) synchronous semiconductor memory devices have been proposed to improve the operation speed thereof. The SDR synchronous semiconductor memory devices may receive or output a single data through a single data pin in one cycle of the external clock signal in synchronization with every rising edge of the external clock signal. However, high performance devices operating at a higher speed than the SDR synchronous semiconductor memory devices have been demanded to meet the requirements of high performance semiconductor systems. Accordingly, double data rate (DDR) synchronous semiconductor memory devices have been recently proposed. DDR synchronous semiconductor memory devices may receive and output data in synchronization with every rising edge and every falling edge of an external clock signal. Thus, DDR synchronous semiconductor memory devices may operate at a speed which is at least twice higher than that of SDR synchronous semiconductor memory devices even without an increase in a frequency of the external clock signal.